p-channel logic level enhancement mode field effect transistor P1403EVG sop-8 halogen-free & lead-free niko - sem 1 jun-22-2010 rev 1.3 absolute maximum ratings (t a = 25 c unless o therwise noted) parameters/test conditions symbol limits units drain-source voltage v ds -30 v gate-source voltage v gs 25 v t a = 25 c -11 continuous drain current t a = 70 c i d -9 pulsed drain current 1 i dm -50 avalanche current i as -43 a avalanche energy l = 0.1mh e as 90 mj t a = 25 c 2.5 power dissipation t a = 70 c p d 1.6 w operating junction & storage temperature range t j , t stg -55 to 150 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-case r j c 25 c / w junction-to-ambient r ja 50 c / w 1 pulse width limited by maximum junction temperature . electrical characteristics (t a = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = -250 a -30 gate threshold voltage v gs(th) v ds = v gs , i d = -250 a -1 -1.7 -3 v gate-body leakage i gss v ds = 0v, v gs = 25v 100 na v ds = -24v, v gs = 0v -1 zero gate voltage drain current i dss v ds = -20v, v gs = 0v, t j = 125 c -10 a 4 :gate 5,6,7,8 :drain 1,2,3 :source product summary v (br)dss r ds(on) i d -30 14m -11 g s d 100% uis tested www.datasheet.co.kr datasheet pdf - http://www..net/
p-channel logic level enhancement mode field effect transistor P1403EVG sop-8 halogen-free & lead-free niko - sem 2 jun-22-2010 rev 1.3 v gs = -4.5v, i d = -9a 14 22 drain-source on-state resistance 1 r ds(on) v gs = -10v, i d = -12a 9 14 m forward transconductance 1 g fs v ds = -10v, i d = -12a 28 s dynamic input capacitance c iss 2510 output capacitance c oss 449 reverse transfer capacitance c rss v gs = 0v, v ds = -15v, f = 1mhz 349 pf gate resistance rg v gs = 0v, v ds = 0v, f = 1mhz 7.3 q g(vgs=10v) 48 total gate charge 2 q g(vgs=4.5v) 26 gate-source charge 2 q gs 7 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = -10v, i d = -12a 9 nc turn-on delay time 2 t d(on) 12 rise time 2 t r v ds = -15v, 16 turn-off delay time 2 t d(off) i d ? -1a, v gs = -10v, r gs = 6 50 fall time 2 t f 100 ns source-drain diode ratings and characteristics (t a = 25 c) continuous current i s -2.1 a forward voltage 1 v sd i f = i s , v gs = 0v -1.2 v 1 pulse test : pulse width 300 sec, duty cycle 2 . 2 independent of operating temperature. remark: the product marked with P1403EVG, date co de or lot # www.datasheet.co.kr datasheet pdf - http://www..net/
p-channel logic level enhancement mode field effect transistor P1403EVG sop-8 halogen-free & lead-free niko - sem 3 jun-22-2010 rev 1.3 0 2 4 6 8 10 0 10 20 30 40 50 i d = 12a v ds = 15v 0 1 2 3 4 5 10 20 30 40 50 v gs = 3v v gs = 4.5v v gs = 7v v gs = 10v 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 v gs = 4.5v v gs = 10v 0 2 4 6 8 10 0 0.01 0.02 0.03 0.04 0.05 i d = -12a - 50 - 25 0 25 50 75 100 125 150 r ds(on) x 0.6 i d = -12a v gs = 10v r ds(on) x 0.8 r ds(on) x 1.0 r ds(on) x 1.2 r ds(on) x 1.4 r ds(on) x 1.6 r ds(on) x 0.4 t j =125 c 0 10 20 30 40 50 t j =-20 c 5.0 2.0 2.5 3.0 3.5 4.0 4.5 t j =25 c v ds = -10v 1.5 1.0 output characteristics -i d , drain-to-source current(a) -v ds , drain-to-source voltage(v) on - resistance vs drain current r ds(on) on-resistance(ohm) - i d , drain - to - source current on - resistance vs gate - to - source r ds(on) on-resistance(ohm) -v gs , gate-to-source voltage(v) on - resistance vs temperature r ds(on) on-resistance(ohm) t j , junction temperature(?c) transfer characteristics -i d , drain-to-source current(a) -v gs , gate-to-source voltage(v) gate charge characteristics characteristics -v gs , gate-to-source voltage(v) qg , total gate charge(nc) www.datasheet.co.kr datasheet pdf - http://www..net/
p-channel logic level enhancement mode field effect transistor P1403EVG sop-8 halogen-free & lead-free niko - sem 4 jun-22-2010 rev 1.3 ciss coss crss 0.00e+00 5.00e-10 1.00e-09 1.50e-09 2.00e-09 2.50e-09 3.00e-09 0 5 10 15 20 25 30 f = 1mhz v gs = 0v 0 100 200 300 400 500 0.0001 0.001 0.01 0.1 1 10 single pulse r ja = 50 ? ?? ? c/w t a =25 ? ?? ? c 100us 10s 1s dc 100ms 10ms 1ms 0.01 0.1 1 10 100 0.1 1 10 100 note : 1.v gs = 10v 2.t a =25 ? ?? ? c 3.r ja = 50 ? ?? ? c/w 4.single pulse operation in this area is lim ited by r ds(on) 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0 1 .2 1 .0 e + 0 1 t j = 1 5 0 c t j = 2 5 c 1 .0 e + 0 0 1 .0 e - 0 1 1 .0 e -0 2 1 .0 e -0 3 1 .0 e -0 4 1 .0 e -0 5 1 .0 e + 0 2 capacitance characteristic c , capacitance(pf) -v ds , drain-to-source voltage(v) body diode forward voltage vs source current -i s , source current(a) -v sd , source-to-drain voltage(v) t 1 , square wave pulse duration[sec] r(t) , normalized effective transient thermal resistance -i d , drain current(a) transient thermal response curve safe operating area -v ds , drain-to-source voltage(v) power(w) single pulse maximum power dissipation www.datasheet.co.kr datasheet pdf - http://www..net/
p-channel logic level enhancement mode field effect transistor P1403EVG sop-8 halogen-free & lead-free niko - sem 5 jun-22-2010 rev 1.3 www.datasheet.co.kr datasheet pdf - http://www..net/
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